FIG. 1 illustrates a pixel 100 of a CMOS image sensor, which is generally known in the art as a 2T5 pixel, as it comprises five transistors and two photodiodes. This circuitry is, for example, described in IEEE publication titled “A 1/2.5 inch 5.2 Mpixel, 96 dB Dynamic Range CMOS Image Sensor with fixed Pattern Noise Free, Double Exposure Time Read-Out Operation”, Yoshitaka Egawa et al.
Circuit 100 comprises photodiodes 101 and 102, connected between ground and first source/drain nodes of respective transistors 104 and 106, which have their second source/drain nodes connected to a node 107. Node 107 is connected to the gate of a transistor 108, which has one of its source/drain nodes connected to a column line 110, and its other source/drain node connected to a supply voltage via a transistor 112. A reset transistor 114 is provided connected between node 107 and the supply voltage.
Photodiodes 101 and 102 are reverse polarized, and their electrical behavior is similar to that of capacitors, allowing a voltage to be stored by them, which is discharged during an integration phase of the image sensor. Charges accumulated are then transferred to the parasitic capacitance of node 107, and the resulting voltage of node 107 can be read via column line 110, by activating transistor 112.
The operation of pixel 100 for capturing and reading image data from photodiode 101 as described by Egawa et al. will now be described with reference to the timing diagrams illustrated in FIG. 2.
Before the start of the integration phase, the reset signal RST is applied to reset the voltage at node 107 to the supply voltage. Signal TG1 at the gate of transistor 104 is then asserted high for a first pulse 201, for example to a voltage of 2.8 V, such that transistor 104 is turned on and photodiode 101 discharges any charge stored by it to the supply via transistors 104 and 114. The internal photodiode potential becomes the natural potential of the photodiode that results from doping, for example equal to around 1.5 V. At the start of an integration phase, TG1 returns low, as shown by falling edge 202 in FIG. 2. The reset transistor 114 remains on.
During the integration phase, electrical charges generated in the photodiode 101 reduce the photodiode voltage. After a determined time period, TG1 is asserted high for a second pulse 203, but to a lower voltage than the first pulse 201. The first pulse has a magnitude of 2.8 V and the second pulse 1.4 V. If the photodiode voltage has fallen during this time to a value below 1.4−VthTG, where VthTG is the threshold voltage of transistor 104, it will be increased again to this level. Otherwise, if it is higher than 1.4−VthTG, it will remain at the corresponding level. Because the reset transistor is still open, node 107 remains at the supply voltage.
At the falling edge of the second pulse, labelled 204 in FIG. 2, a short integration period starts, in which the photodiode voltage continues to fall due to charge generated by exposure to light of the photodiode. The signal RST is then lowered to isolate node 107 from the supply voltage. The short integration phase is ended by a third pulse 205 applied to TG1 having the same low amplitude as the second pulse 203, for example 1.4 V. Thus, if during the short integration phase the photodiode voltage has fallen to less than 1.4−VthTG, the voltage at node 107 will decrease accordingly, and the photodiode voltage will be returned to 1.4−VthTG. The voltage at node 107 is then read, as indicated by arrow L1 in FIG. 2, by activating transistor 112, such that the voltage is output on column line 110. This first voltage is digitalized into a 16-bit value.
Next, the voltage at node 107 is reset by activating and then deactivating the reset transistor 114, and a fourth pulse 207 is applied to TG1 having a high amplitude of 2.8 V. The voltage at node 107 is then altered by the total charge accumulated by the photodiode. After the falling edge of the fourth pulse, labelled 210 in FIG. 2, the voltage at node 107 is again read as indicated by arrow L2. Transistor 112 is activated and outputs the voltage at node 107 to column line 110. This voltage level is digitalized to generate a 16-bit value.
The two reads as described above are performed on each row of pixels of the image sensor, and are stored in memory. The memory required for this is therefore the memory that would normally store two rows of image data. If the reading at L1 is V1 and the reading at L2 is V2, the final output is then determined as the highest value between V1+V2 and V1(TL/TS), where TL is the overall time duration of the long integration period and TC is the time duration of the short integration period, these values being illustrated in FIG. 2. White balance and color reconstruction are then performed, and then compression to generate a 12-bit value for each pixel.
The method proposed by Egawa et al. allows the dynamic range of the pixel to be increased by a certain extent using two digitalizations following two reads.
It would be desirable to provide an improved method and circuitry that increases the dynamic range of the image sensor further.